The present invention relates to the preparation of semiconductor device structures. More particularly, the present invention pertains to methods of forming conductive structures such as electrode structures and the structures resulting therefrom.
In the fabrication of integrated circuits, various conductive layers are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), or any other types of memory devices, conductive materials are used in the formation of storage cell capacitors, and also may be used in interconnection structures, e.g., conductive layers in contact holes, vias, etc. For example, in the fabrication of integrated circuits including capacitor structures, conductive layers are used for capacitor electrodes. Memory circuits, such as DRAMs and the like, use conductive structures to form opposing electrodes of storage cell capacitors.
As memory devices become more dense, it is necessary to decrease the size of circuit components forming such devices. One way to retain storage capacity of storage cell capacitors of the memory devices, and at the same time decrease the memory device size, is to increase the dielectric constant of the dielectric layer of a storage cell capacitor. Therefore, high dielectric constant materials are used in such applications and interposed between two electrodes. One or more layers of various conductive materials may be used as the electrode material. Generally, one or more of the layers of conductive material used for the electrodes (particularly the bottom electrode of the cell capacitor) has certain diffusion barrier properties, e.g., silicon or oxygen diffusion barrier properties. Such properties are particularly required when high dielectric constant materials are used for the dielectric layer of the storage cell capacitor because of the processes used in forming such high dielectric constant materials, e.g., deposition of high dielectric constant materials usually occurs at high temperatures (generally, greater than about 500xc2x0 C.) in an oxygen-containing atmosphere.
Various metals and metallic compounds, for example, metals such as platinum, and conductive metal oxides such as ruthenium oxide, have been proposed as the electrode materials or at least one of the layers of an electrode stack for use with high dielectric constant materials. However, electrodes generally need to be constructed such that they do not diminish the beneficial properties of the high dielectric constant materials. For example, for platinum to function well as a bottom electrode or as one of the layers of an electrode stack, an effective barrier to the diffusion of silicon from the substrate or other silicon-containing region to the top of the electrode needs to be provided. This is typically required since silicon at the surface of the electrode stack will tend to be oxidized during the oxygen anneal of the high dielectric constant materials and/or during deposition of oxide dielectrics, e.g., Ta2O5 or BaSrTiO3, which will result in a decreased series capacitance, thus degrading the storage capacity of the capacitor. In addition, oxygen diffusion through the platinum electrode layer during high temperature oxidizing processes, e.g., BaSrTiO3 deposition processes, needs to be prevented. Such oxygen diffusion through the platinum occurs generally through the platinum grain boundaries.
Further, during high temperature processing of devices (e.g., high dielectric constant material formation processes) that include platinum conductive layers, stress occurs in the platinum layer. Such stress may result in the formation of a discontinuous platinum layer, such as in the form of platinum islands, which are undesirable. The formation of such platinum islands may result in films that are unstable for use as capacitor electrodes.
In addition to the use of high dielectric constant materials for capacitor structures, it is desirable to take other steps to increase or preserve capacitance without increasing the occupied area. For example, electrode surfaces may be roughened to increase the effective surface area of electrodes without increasing the area occupied by the capacitor.
One method for providing a roughened surface for a plate of a storage cell capacitor is to form the plate of hemispherical grain polysilicon (HSG), possibly with an overlying metal layer. The hemispherical grains of HSG enhance the surface area of the plate without increasing its occupied area.
However, HSG presents difficulties in fabrication because of the formation of silicon dioxide on and near the HSG. A silicon dioxide layer may form on the HSG, particularly during deposition of the capacitor""s dielectric layer. Even with an intervening metal layer present, oxygen from the deposition of the dielectric layer can diffuse through the metal layer, forming silicon dioxide at the polysilicon surface. Silicon diffusion through the metal layer may also produce an undesirable silicon dioxide layer between the metal and the dielectric layers.
To avoid these negative effects caused by formation of silicon dioxide, a diffusion barrier layer may be employed between the HSG and the metal layer. But, in a typical capacitor geometry, the greater the total number of layers, the larger the required minimum area occupied by the capacitor. Further, the upper surface of each additional layer deposited over the HSG tends to be smoother than the underlying surface, reducing the increased surface area provided by the HSG.
The present invention provides a stable metal/metal oxide structure (e.g., a platinum/ruthenium oxide composite structure) for use in integrated circuits, e.g., capacitor electrodes. Such a metal/metal oxide composite structure is especially beneficial for use with high permittivity materials, e.g., high dielectric constant materials used with capacitor structures. Further, the present invention also provides for an enhanced surface area electrode.
A method for use in fabrication of integrated circuits according to the present invention includes providing a substrate assembly including an oxygen-containing surface portion and forming a first metal layer on at least a portion of the oxygen-containing surface portion. A second metal layer is formed on at least a portion of the first metal layer and an oxidation diffusion barrier layer is provided on at least a portion of the second metal layer. One or more regions of the second metal layer are oxidized to form metal oxide regions corresponding to one or more grain boundaries of the first metal layer by thermally treating the substrate assembly having the first metal layer, second metal layer, and oxidation diffusion barrier layer formed thereon. The oxidation diffusion barrier layer and unoxidized portions of the second metal layer are then removed.
In another method for use in fabrication of integrated circuits according to the present invention, a substrate assembly including an oxygen-containing surface portion is provided and a first metal layer (e.g., platinum) is formed on at least a portion of the oxygen-containing surface portion. The first metal layer has grain boundaries extending therethrough. A second metal layer (e.g., ruthenium) is formed on at least a portion of the first metal layer. Metal oxide regions are formed on at least portions of the first metal layer at one or more grain boundaries thereof through selective oxidation of the second metal layer by diffusion of oxygen from the oxygen-containing surface portion through the one or more grain boundaries of the first metal layer. For example, the metal oxide regions may be formed by providing an oxidation diffusion barrier layer on at least a portion of the second metal layer, thermally treating the substrate assembly having the first metal layer, second metal layer, and oxidation diffusion barrier layer formed thereon to selectively oxidize one or more regions of the second metal layer at the one or more grain boundaries of the first metal layer resulting in the one or more metal oxide regions and unoxidized portions of the second metal layer therebetween, and then removing the oxidation diffusion barrier layer and the unoxidized portions of the second metal layer.
In various embodiments of the methods, the thermal treatment may be performed at a temperature greater than 300xc2x0 C., the thermal treatment may be performed in a non-oxidizing atmosphere, the first metal layer may be formed of at least one metal selected from the group of platinum, palladium, rhodium, and iridium (preferably platinum), the second metal layer may be formed of at least one metal selected from the group of ruthenium, osmium, rhodium, iridium, and cerium (preferably ruthenium), the oxidation diffusion barrier layer may be formed of at least one of silicon nitride, silicon oxynitride, and aluminum oxide (preferably silicon nitride), and the unoxidized portions of the second metal layer may be removed using at least one of a wet etch and a dry etch. Yet further, in other embodiments, the methods above may be used in the formation of capacitors, e.g., electrodes thereof.
A semiconductor structure according to the present invention includes a substrate assembly including an oxygen-containing surface portion and a first metal layer (e.g., platinum) on at least a portion of the oxygen-containing surface portion. One or more metal oxide regions (e.g., ruthenium oxide) are formed from a second metal layer on at least portions of the first metal layer at one or more grain boundaries thereof.
In one embodiment of the structure, the structure includes an oxidation diffusion barrier layer on at least a portion of the second metal layer over at least the one or more metal oxide regions and unoxidized portions of the second metal layer between the one or more metal oxide regions.
In various other embodiments of the structure, the oxidation diffusion barrier layer may be formed of at least one of silicon nitride, silicon oxynitride, and aluminum oxide, the first metal layer may be formed of at least one metal selected from the group of platinum, palladium, rhodium, and iridium (preferably platinum), and the second metal layer may be formed of at least one metal selected from the group of ruthenium, osmium, rhodium, iridium, and cerium (preferably ruthenium).
Further, in other embodiments of the structure, the structure may be used as part of or in the formation of a capacitor structure and/or a memory cell structure.